5-輸入 1-AND邏輯閘

<5-輸入 1-AND邏輯閘>
module top;

wire A, B, C, D, E, OUT
system_clock #400 clock1(A);
system_clock #200 clock2(B);
system_clock #600 clock3(C);
system_clock #200 clock4(D);
system_clock #400 clock5(E);

and a1(OUT, A, B, C, D, E);


endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

5-輸入 4-AND邏輯閘

<5-輸入 4-AND邏輯閘>

module top;

wire A, B, C, D, E, OUT, OUT2, OUT3 ,OUT4
system_clock #400 clock1(A);
system_clock #200 clock2(B);
system_clock #600 clock3(C);
system_clock #200 clock4(D);
system_clock #400 clock5(E);

and a1(OUT, A, B);
and a2(OUT2, OUT, C);
and a3(OUT3, D, C);
and a4(OUT4, OUT2, OUT3);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

3-輸入 2-AND邏輯閘

<3-輸入 2-AND邏輯閘>
module top;

wire A, B, C, OUT,OUT2
system_clock #400 clock1(A);
system_clock #200 clock2(B);
system_clock #600 clock3(C);


and a1(OUT, A, B);
and a2(OUT2, OUT, C);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule