一位元加法器行為模式設計與測試/ P29化簡

module test_adder1;

 reg a,b
 reg carry_in
 wire sum;
 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial
  begin

    carry_in = 0; a = 0; b = 0;
    # 100 if ( carry_out !== 0 | sum !== 0)
                $display(" 0+0+0=00 sum is WRONG!");
              else
                $display(" 0+0+0=00 sum is RIGHT!");
    carry_in = 0; a = 0; b = 1;
    # 100 if ( carry_out !== 0 | sum !== 1)
               $display(" 0+0+1=01 sum is WRONG!");
              else
               $display(" 0+0+1=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 0;
    # 100 if ( carry_out !== 0 | sum !== 1)
               $display(" 0+1+0=01 sum is WRONG!");
              else
               $display(" 0+1+0=01 sum is RIGHT!");
    carry_in = 1; a = 0; b = 0;
    # 100 if ( carry_out !== 0 | sum !== 1)
               $display(" 1+0+0=01 sum is WRONG!");
              else
               $display(" 1+0+0=01 sum is RIGHT!");
    carry_in = 1; a = 0; b = 1;
    # 100 if ( carry_out !== 0 | sum !== 1)
               $display(" 1+0+1=10 sum is WRONG!");
              else
               $display(" 1+0+1=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0;
    # 100 if ( carry_out !== 0 | sum !== 1)
               $display(" 1+1+0=10 sum is WRONG!");
              else
               $display(" 1+1+0=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 1;
    # 100 if ( carry_out !== 1 | sum !== 1)
               $display(" 1+1+1=11 sum is WRONG!");
              else
               $display(" 1+1+1=11 sum is RIGHT!");
    $finish;
  end
endmodule

input a, b, carry_in;

output carry_out, sum;

assign sum = (a^b)^carry_in;

assign carry_out = (a^b)&carry_in|(a&b);

endmodule

一位元加法器行為模式設計與測試

module test_adder1;

 reg a,b
 reg carry_in
 wire sum;
 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial
  begin

    carry_in = 0; a = 0; b = 0;
    # 100 if ( carry_out !== 0 | sum !== 0)
                $display(" 0+0+0=00 sum is WRONG!");
              else
                $display(" 0+0+0=00 sum is RIGHT!");
    carry_in = 0; a = 0; b = 1;
    # 100 if ( carry_out !== 0 | sum !== 1)
               $display(" 0+0+1=01 sum is WRONG!");
              else
               $display(" 0+0+1=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 0;
    # 100 if ( carry_out !== 0 | sum !== 1)
               $display(" 0+1+0=01 sum is WRONG!");
              else
               $display(" 0+1+0=01 sum is RIGHT!");
    carry_in = 1; a = 0; b = 0;
    # 100 if ( carry_out !== 0 | sum !== 1)
               $display(" 1+0+0=01 sum is WRONG!");
              else
               $display(" 1+0+0=01 sum is RIGHT!");
    carry_in = 1; a = 0; b = 1;
    # 100 if ( carry_out !== 0 | sum !== 1)
               $display(" 1+0+1=10 sum is WRONG!");
              else
               $display(" 1+0+1=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0;
    # 100 if ( carry_out !== 0 | sum !== 1)
               $display(" 1+1+0=10 sum is WRONG!");
              else
               $display(" 1+1+0=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 1;
    # 100 if ( carry_out !== 1 | sum !== 1)
               $display(" 1+1+1=11 sum is WRONG!");
              else
               $display(" 1+1+1=11 sum is RIGHT!");
    $finish;
  end
endmodule



module adder1_behavorial (carry_out, sum, a, b, carry_in);
 input a, b, carry_in;
 output carry_out, sum;
  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in);
  assign carry_out = a&carry_in|a&b|b&carry_in;
endmodule

六位元多工器 結構模式

module top;

wire [5:0]A, B,OUT
wire SEL;
system_clock #100 clock1(A[0]);
system_clock #110 clock2(A[1]);
system_clock #120 clock3(A[2]);
system_clock #130 clock8(A[3]);
system_clock #140 clock12(A[4]);
system_clock #150 clock13(A[5]);
system_clock #200 clock4(B[0]);
system_clock #210 clock5(B[1]);
system_clock #220 clock6(B[2]);
system_clock #230 clock9(B[3]);
system_clock #240 clock10(B[4]);
system_clock #250 clock11(B[5]);
system_clock #400 clock7(SEL);

mux2 M1  (OUT, A, B, SEL);
endmodule

module mux(OUT, A, B, SEL);

output OUT;
input A,B,SEL;

not I5 (sel_n, SEL) ;
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule

module mux2(OUT, A, B, SEL);
output [5:0] OUT;
input [5:0] A,B;
input SEL;
mux hi (OUT[5], A[5], B[5], SEL);
mux middle1(OUT[4], A[4], B[4], SEL);
mux middle2(OUT[3], A[3], B[3], SEL);
mux middle3(OUT[2], A[2], B[2], SEL);
mux middle4(OUT[1], A[1], B[1], SEL);
mux lo (OUT[0], A[0], B[0], SEL);
endmodule



module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>7000)$stop;

endmodule

三位元多工器 結構模式

module top;

wire [2:0]A, B,OUT
wire SEL;
system_clock #100 clock1(A[0]);
system_clock #100 clock2(A[1]);
system_clock #100 clock3(A[2]);
system_clock #200 clock4(B[0]);
system_clock #200 clock5(B[1]);
system_clock #200 clock6(B[2]);
system_clock #400 clock7(SEL);

mux2 M1  (OUT, A, B, SEL);
endmodule

module mux(OUT, A, B, SEL);

output OUT;
input A,B,SEL;

not I5 (sel_n, SEL) ;
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule

module mux2(OUT, A, B, SEL);
output [2:0] OUT;
input [2:0] A,B;
input SEL;
mux hi (OUT[2], A[2], B[2], SEL);
mux middle (OUT[1], A[1], B[1], SEL);
mux lo (OUT[0], A[0], B[0], SEL);
endmodule


module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule