六位元多工器 結構模式

module top;

wire [5:0]A, B,OUT
wire SEL;
system_clock #100 clock1(A[0]);
system_clock #110 clock2(A[1]);
system_clock #120 clock3(A[2]);
system_clock #130 clock8(A[3]);
system_clock #140 clock12(A[4]);
system_clock #150 clock13(A[5]);
system_clock #200 clock4(B[0]);
system_clock #210 clock5(B[1]);
system_clock #220 clock6(B[2]);
system_clock #230 clock9(B[3]);
system_clock #240 clock10(B[4]);
system_clock #250 clock11(B[5]);
system_clock #400 clock7(SEL);

mux2 M1  (OUT, A, B, SEL);
endmodule

module mux(OUT, A, B, SEL);

output OUT;
input A,B,SEL;

not I5 (sel_n, SEL) ;
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule

module mux2(OUT, A, B, SEL);
output [5:0] OUT;
input [5:0] A,B;
input SEL;
mux hi (OUT[5], A[5], B[5], SEL);
mux middle1(OUT[4], A[4], B[4], SEL);
mux middle2(OUT[3], A[3], B[3], SEL);
mux middle3(OUT[2], A[2], B[2], SEL);
mux middle4(OUT[1], A[1], B[1], SEL);
mux lo (OUT[0], A[0], B[0], SEL);
endmodule



module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>7000)$stop;

endmodule